🚀 go-pugleaf

jso...@marcam.com (Jeff Somers) wrote:
>In article <43qam8$p...@pellew.ntu.edu.au>, nobody <nob...@csufresno.edu> writes:
>[cut]
>|> 
>|>    Intel P6, AMD K5, and NexGen 586 are all RISC processors   emulating 
>|>   X86.(hell, you can even feed them their native RISC instuctions and   
>|>   bypass X86 instructions entirely). Only Cyrix's M1 is the true X86   
>|>   processor with CISC core.
>[cut]
>
>Not true, the P6 won't allow you to do that.  (Forget where I read this;
>probably either Byte or PC Mag.)  I can see why, too, it would force 
>Intel to be backwards compatible with another instruction set.  It 
>would be difficult for them tweak their "risc instruction set" for the
>P7 and beyond if everyone was bypassing the 386 instruction set.

  It is possible to feed P6, K5, and Nx586 with their native RISC 
instructions, but Intel will not document the P6 RISC instructions, since 
that was for internal testing purpose only(There are lots of stuffs in 
X86 architectures that intel won't document, like extra resisters and 
instructions). Beside, nobody is going to write the applications in X86 
emulators' native instructions, since that would limit the market 
severely.   



>
>jeff s.
>jso...@marcam.com