🚀 go-pugleaf

nobody <nob...@csufresno.edu> wrote:


>  It is possible to feed P6, K5, and Nx586 with their native RISC 
>instructions, but Intel will not document the P6 RISC instructions, since 
>that was for internal testing purpose only(There are lots of stuffs in 
>X86 architectures that intel won't document, like extra resisters and 
>instructions). Beside, nobody is going to write the applications in X86 
>emulators' native instructions, since that would limit the market 
>severely.   

I need not respond to your "rebuttal" (of sorts), as thankfully
another user spared me the pain (or rather, humour) in correcting your
wild, er, "unique" point of view on modern microprocessor design.

They are NO "native" instructions for the P6, K5, and Nx586.  They do
not EMULATE.  They simply translate X86 instrucions into "micro-ops"
to facilitate better handling and breakdown in the pipeline.  Get it
through your head.  Put down EGM, and read a book.