🚀 go-pugleaf

On Wednesday, March 7, 2018 at 8:27:38 PM UTC-7, Mike Spencer wrote:
 
> Thank you.  I understood nore than half of that.  Might get even more
> on re-reading.

You're welcome.

Although I tried to be clear, I do realize that I probably assumed a lot of 
knowledge about the inner workings of computers, so I think that maybe I can do 
even better.

A long time ago, big computers made from transistors were pipelined, such as the IBM 7094 II or the SDS 9300. What this meant was basically the same thing as you might do when doing laundry - while one load of clothes is in the washer, the previous load is in the dryer.

With those early machines, the actions taken in response to a machine 
instruction were divided into three stages: Fetch, Decode, and Execute. While 
one instruction is actually being performed in the Execute stage, the next 
one can be Decoded by the computer, and the one after can be Fetched from 
memory.

This was simple and unproblematic; the Execute stages of the consecutive 
instructions still didn't overlap, so if one instruction depended on the 
result of the previous one - which is the usual way most programs are written 
- there would be no difficulty as a result.

Later on, though, more advanced computers were designed that attempted to 
speed things up even more, allowing more instructions to be worked on at 
once, by splitting up doing the instruction into smaller pieces.

If you split the Execute portion up into more than one piece, though, then 
you can't have consecutive instructions depending on one another. There are 
two ways around this - have a lot of registers, so that you can write your 
program with sequences of instructions working on different things that are 
interleaved - or use "out-of-order execution" with "register renaming" (or 
the equivalent, reservation stations) where the computer looks ahead for a 
part of your program doing something different, and interleaves it in, using 
extra registers to make up for the fact that the later part of the program is 
re-using the same registers.

The Pentium II did this, and so do Core processors, and so did the Pentium 4. 
The difference is that the Pentium 4 cut the Execute stage up into even 
smaller bits.

The other major piece of this story is that today's microprocessors are all 
made using CMOS. CMOS doesn't use as much power as other logic families. It 
takes power to switch from "on" to "off", but in between, when the input 
signals aren't changing, everything is either an open circuit or a closed 
circuit, with no resistors dissipating energy, so except for unavoidable 
things like leakage and wire resistance, it doesn't use power.

When you cut the Execute stage up into smaller bits - each bit, each pipeline 
stage, represents a *new input* for the logic gates in that stage. Stage 5 of 
an addition, on one clock cycle, was fed signals for adding the two numbers 
that a certain instruction was adding; on the next clock, it will be fed 
signals for the numbers a later add instruction will work on.

So if in design A, there were 16 logic gates per pipeline stage, and in 
design B, there were 12 logic gates per pipeline stage... in design A, 1/16 
of the transistors are "doing something" and making heat, and in design B, 
1/12 of them are "doing something" and making heat. So design B dissipates 1 
1/3 times as many watts as design A.

Now comes the part were the mysterious phrase "Dennard scaling", which you 
might not have heard before, comes in. It's not as commonly used as "Moore's 
Law", but it explains why processors haven't gotten faster than 4 GHz for 
years now, so they went to dual-core, four-core, and now eight cores with 
Ryzen instead.

Moore's Law - twice as many transistors on a chip every 18 months - was a 
result of them finding ways to make the transistors smaller and smaller as 
time went on.

Smaller transistors were also *better*. They didn't use as much power, and 
they worked faster. That was what was called "Dennard scaling".

Well, at about the 65nm process point, smaller transistors... no longer got 
as much better. After 65nm, as feature size shrunk still more, the 
transistors still got a little better, but not as much.

The Pentium 4 was an attempt to make a computer chip go faster by making a bigger fraction of its transistors work at any one time. That made it run hotter. While one might think that since transistors didn't start getting _worse_ as feature size got smaller, if it worked at one feature size, the design should have still worked in later processes as well...

basically, the Pentium 4 was skating close to the edge at the time it was 
brought out, and _if_ transistors weren't going to be getting better as fast 
as expected, instead of it being far from the edge in the next generation - 
and thus the kind of thing needed in the future, with later developments 
going even further in the same direction -

instead, it was always going to be on the edge, so it couldn't be changed 
much and improved still further. So it made more sense to go back to the 
Pentium III design, and find ways to improve that in a *different* direction 
that could still be further and further developed over time year after year 
to make better and better processors.

So they went to Core 2, Core 2 Duo, and eventually Core 2 Quad. Because the 
Pentium III design ran cooler, they could put four of them on one chip, while 
with the Pentium 4, they managed two.

Maybe this explains some things I glossed over previously.

John Savard