🚀 go-pugleaf

Peter Flass <peter...@yahoo.com> writes:
> Cable length was the big problem. If you put the core too far from the CPU
> you had to go with slow memory. Each <mumble>K of core needed its own
> frame. One of the larger machines had the boxes of core arranged in an "X"
> around the CPU to try to reduce cable length. I'm not sure about core, but
> I think some large shops put disk controllers one floor down from the CPU
> and dropped the channel cables thru the floor to reduce distance.

packaging distance ... happened for 3090 ... plus some 3880 disk
controller channel overhead. 3880/3380 increased transfer speed but also
doubled max. channel cable distance (by expanding number of bytes
transferred in single handshake). however they went from a very fast
horizontal microcode controller for 3830 to a very slow verticial
microcode controller for 3880 ... with a hardware side-path for data
transfer. The increased data transfer reduced channel busy, but the
increased 3880 controller overhead more than offset the increased
transfer speed.

3090 assumed 3880 would be same as 3830 controller but with 3380
3mbyte/sec transfer ... however 3880 controller operations were
significantly slower ... significantly driving up channel busy.  As a
result, 3090 trying to have balanced throughput configuration had to
significantly increase number of channels as (partial) offset to the
signifciantly higher 3880 channel busy (which required additional
expensive TCM, joke was 3090 would charge off the manufacturing cost for
the additional TCM to the 3880 controller group). Marketing then try to
resping the enormous increase as channels as terrific I/O capability
(when it was somewhat the opposite).

Also needed significantly more real storage for caching more data &
pages ... helping reduce needed 3880 disk I/O. However, the packaging
distance for the additional real storage exceeded processor memory spec
latency. As a result they came up with "expanded store" wide fast bus
with the higher latency but treated as electronic paging devices with
syncronous 4k move to/from instruction (elapsed time for syncrhonous
move instruction was orders of magnitude less than MVS IO+interrupt
pathlength).

Note 3090 trying to move into scientific market ... addeded vector
processing feature/registers/instructions ... but scientific market also
had HIPPI (100mbyte/sec channel) disk arrays
https://en.wikipedia.org/wiki/HIPPI

3090 I/O wasn't even remotely capable of handling HIPPI speeds. They
finally came up with rube goldberg hack that cut HIPPI into the side of
expanded store bus ... using the synchronous transfer instruction for
peak/poke i/o paradigm.

3090
http://www.bitsavers.com/pdf/ibm/3090/G580-1005-0_The_IBM_3090_Processor_Family_Jul87.pdf
3090 principles of op (1403/3211 printer version)
http://www.bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf

about the time the scientific group in kingston was cutting HIPPI into
the 3090 expanded store bus, I was also working with high-speed access
into Clementi's engineering & scientific kingston lab with half dozen
floating post system boxes (with disk arrays, which may have helped spur
the effort to hook disk arrays into 3090). misc. past posts mentioning
Clementi:
http://www.garlic.com/~lynn/2013i.html#14 The cloud is killing traditional hardware and software
http://www.garlic.com/~lynn/2014b.html#4 IBM Plans Big Spending for the Cloud ($1.2B)
http://www.garlic.com/~lynn/2014c.html#63 11 Years to Catch Up with Seymour
http://www.garlic.com/~lynn/2014c.html#72 11 Years to Catch Up with Seymour
http://www.garlic.com/~lynn/2014j.html#35 curly brace languages source code style quides
http://www.garlic.com/~lynn/2016e.html#95 IBM History
http://www.garlic.com/~lynn/2017h.html#50 System/360--detailed engineering description (AFIPS 1964)
http://www.garlic.com/~lynn/2017j.html#92 mainframe fortran, or A Computer That Never Was: the IBM 7095
http://www.garlic.com/~lynn/2018b.html#47 Think you know web browsers? Take this quiz and prove it

past posts mentioning having HSDT project doing T1 & faster links
http://www.garilc.com/~lynn/subnetwork.html#hsdt
including working with director of NSF for high speed links for
NSF supercomputer centers ... misc. old email
http://www.garlic.com/~lynn/lhwemail.html#nsfnet


-- 
virtualization experience starting Jan1968, online at home since Mar1970