🚀 go-pugleaf

hanc...@bbs.cpcn.com writes:
> From what I've read, creating a compatible product line across
> all four modes* in 1960 would require a lot of compromises that
> would downgrade performance and increase cost.  In 1960, computer
> hardware was still extremely expensive, not that fast, so including
> circuits to do unwanted functions was an unnecessary expense.  Indeed,
> even in the early days of S/360 and even PC's, floating point was an
> optional feature.  The addressing needs on a small machine are different
> than a large machine; S/360 base+displacement was a compromise.

re:
http://www.garlic.com/~lynn/2018c.html#15 Old word processors
http://www.garlic.com/~lynn/2018c.html#16 Old word processors

claim was that in that emerging computing market, compatibility
outweighed model performance advantage.

majority of 360s were microprogrammed ... so it wasn't all those
circuits.

don't know much about 360 microprogramming ... a little more about
115-II/125-II and 138/148. they avg. 10 native instructions for every
(simulated 370).

115/125 was done by boeblingen (germany) ... it was nine-position memory
bus, 115 had all microprocessors the same ... but with different
microcode loads, 370 instruction, controlleres, etc.  125 was the
identical except the processor running 370 instructions was 50% faster
than the others. 115 was about 800kips processor doing 370 at about
80kips (1/10), 125 was about 1.2mips, doing 370 at 120kips. boeblingen
got their hands "slapped" for doing general 9 position memory bus
implementation.

I got sucked into doing design for 5-way 125 smp that had five of the
processors running 370 microcode (that never shipped). some past
posts
http://www.garlic.com/~lynn/submain.html#bounce
general SMP posts
http://www.garlic.com/~lynn/subtopic.html#smp

about same time, Endicott sucked me into ECPS ... that wanted highest
used 6kbytes of kernel instructions to drop into microcode. following is
study I did ... showing kernel instructions segments sorted by percent
of kernel CPU (6k bytes accounted for 79.55% of kernel CPU execution)
http://www.garlic.com/~lynn/94.html#21 370 ECPS VM microcode assist

FS posts
http://www.garlic.com/~lynn/submain.html#futuresys

at about same time FS imploded and there was mad rush to get products
back into 370 pipeline ... kick off 3033 and 3081 about the same time
http://www.jfsowa.com/computer/memo125.htm

they took 370/158 with integrated channel and removed the 370 microcode
and used 158 engine with just the integrated channel microcode for
external 303x channel director (six channels). A 3031 then was 158
engine with just the 370 microcode and 2nd 158 engine with just the
integrated channel microcode (channel director and a 2-way 3031 smp was
four 158 engines). A 3032 was 168-3 repackaged to use channel
director(s) as external channels (replacing 2860, 2870, 2880). A 3033
then was 168-3 logic remapped to 20% faster chips.

I periodically claimed that father of risc in the mid-70s did risc the
exact opposite of FS (using FS as example of how not to do something).
Circa 1980, 801/risc Iliad was to be the wide variety of internal
microprocessors used in controllers, 370, etc. ... AS/400 followon to
s/36&s/38, 4361&4381 followon toe 4331&4341, etc ... then for various
reasons all these efforts imploded and things returned to standard
customer CISC (and some number of Iliad chip engineers left for risc
projects at other vendors). 801/risc posts
http://www.garlic.com/~lynn/subtopic.html#801

earlier posts in this thread
http://www.garlic.com/~lynn/2018b.html#94 Old word processors
http://www.garlic.com/~lynn/2018b.html#100 Old word processors
http://www.garlic.com/~lynn/2018b.html#103 Old word processors
http://www.garlic.com/~lynn/2018b.html#109 Old word processors
http://www.garlic.com/~lynn/2018c.html#1 Old word processors
http://www.garlic.com/~lynn/2018c.html#7 Old word processors

-- 
virtualization experience starting Jan1968, online at home since Mar1970