🚀 go-pugleaf

Gareth's Downstairs Computer
<headstone255.but.n...@yahoo.com> writes:

> On 25/01/2018 13:00, Dan Espen wrote:
>> Quadibloc <jsa...@ecn.ab.ca> writes:
>>
>>> On Wednesday, January 24, 2018 at 2:43:49 PM UTC-7, han...@bbs.cpcn.com wrote:
>>>> I think the 1460 was totally
>>>> compatible, while the 1410 required a mode switch while its
>>>> native-mode programs were similar, but not compatible.
>>>
>>> I'm not sure of the model number, but I know there indeed was a machine related
>>> to the 1401 but not compatible: the address fields in instructions were five
>>> characters long instead of three.
>>
>> That's the 1410.  It could run with 3 character addresses or 5 character
>> addresses.
>>
>> The 1410 5 character address was accounted for in the 1401 with the
>> placement of the 1401 index registers in memory at locations:
>>
>> 087-089, 092-094 and 097-099
>>
>> Clearly the slack 2 characters between each register were to account for
>> the 1410 5 character index.
>
> Does that mean decimal addressing?

Close, but the 1401 could address 16K with the three characters.
Addresses ran from 001 to 999, then the first char started adding bits.
With BCD you had 2 extra bits for higher addresses so first you turned
on just the A bit, then the B bit, then both the bits.  Then you did the
same thing to the low order character.  The BA bits on the middle
character were for the 3 index registers.  So, 3 character address
"ZZZ" was 15999 plus index register 3.

The size of fields was determined by the word mark.
Just for fun, on an 8K 1440 I wrote code that repetitively
added 1 to an almost 8K digit number.  You could easily watch
the console lights increment through the 8K address for each add.

To add 1 to an 8K number was something like:

      ORG 300
ONE   DC  '1'
START CS  15999     clear storage at top
      CHAIN 156     clear storage down to 300*
      SW  300       set word mark at begin
ADD   A   15999,ONE add 1 to really large number
      B   ADD

* Not responsible for any off by 1 errors.

The CHAIN mnemonic just repeated the OP CODE for the
previous instruction as often as you specified, so
"CHAIN 156" is 156 CS instructions.  Each used the
"A address" from the previous instruction.

The word mark was usually described using an underscore.

A really nice thing about the architecture was that you could
omit addresses from instructions, the machine would use the last
address it referenced.  So for a set of accumulators you could:


      ORG 300
AMT1  DC '000000'
AMT2  DC '000'
AMT3  DC '00000000'
AMT4  DC '00000000'
      ORG 400
TOT1  DC '000000'
TOT2  DC '000'
TOT3  DC '000000000'  note longer fields in totals
TOT4  DC '000000000'

      A  TOT4,AMT4
      A
      A
      A

which looked like this in memory:

      _A423325_A_A_A

On these smaller machines, this could be used
to save oodles of memory.

The S/360 salesman did not appreciate it when
I pointed out that we couldn't even come close
to replacing our 8K 1440 with an 16K S/360.

-- 
Dan Espen