🚀 go-pugleaf

ab...@FreeNet.Carleton.CA (Heinz W. Wiggeshoff) writes:
>  In the very early 70's, I read about a GE 6xx(?) list processing machine
>  instruction.  Someone commented that complier writers like those types
>  of instructions.  Any GE experts in a.f.c-land?

Perhaps you mean an instruction using indirection and then index tally words?
I have a GE 635 manual to check the details if we can identify the instruction.

Or perhaps it was an EIS instruction (a commercial inst. set added to the base
accumulator machine architecture).

I don't believe the 645/Multics added anything like this.



						IBM 1401
						 |
			    625 (1964)		 |
			   / | \		 |
			635  |	615             Honeywell 200
		 .------'    |	 |		 |
transistors	645	     |	605 (military)	 |
- - - - - - - -  |  - - - -  |  - - - - - - - -  |  - - - - - - - - - - -
integrated	 |	    655 (1969)		 |
circuits	 |	     |			 |		IBM S/3
(wire wrap)	6180	    6000		 |		 |
- - - - - - - -  |  - - - -  |  - - - - - - - -  |  - - - - - -  |  - - -
printed		Level 68    Level 66		Level 64	Level 62
circuit		 |	     |			 |
boards		DPS-8       DPS-6		DPS-7



Model designators for the Series 6000

           non-EIS   EIS    EIS = extended instruction set,
           -------  ----          supported business d.p. (COBOL)
slower   /  6010    6020
 versions\  6030    6040
standard    6050    6060
w/cache     6070    6080


The non-Multics 6xx series had 18-bit addressability (the granularity of
  which was 36-bit word), and used the relocation register.  There were
  two modes of execution: master/slave.  OS entry was accomplished by a
  MME instruction (master mode entry).

645 Multics used 24-bit addressability and added a third execution mode:
  absolute.  Absolute mode used physical addressing, while master and
  slave used virtual addressing via the segmentation and paging scheme.


Non-Multics 6xx addressing modes
  R  - register - use index register specified in tag field
  RI - register then indirect (multiple levels of indirection possible)
  IR - indirect then register (multiple levels of indirection possible)
  IT - indirect then tally (tally controlled character manipulation in
       this word-oriented machine)


6xx added several interesting "meta" instructions:
  execute, execute double
  repeat, repeat link, repeat double


Non-Multics 6xx Registers
  72-bit AQ
  eight 18-bit index registers Xn
  8-bit exponent register
  18-bit indicator register
  24-bit timer register
  18-bit instruction address register
  18-bit base address register BAR (relocation register)
        0     7   9     16
       +-------+-+--------+-+
       | base  |0| blocks |0|  blocks = # 1024-word blocks allocated
       +-------+-+--------+-+


645 Multics added eight 24-bit base registers linked in four pairs (these
  were locked to prevent access in slave mode), an 18-bit procedure base
  register, an 18-bit temporary base register, and a 29-bit descriptor
  base register.


Level 66 extended the relocation register by 6 bits to achieve a 16M
  physical address space, although user processes still had an 18-bit
  limit.


-- 
Mark Smotherman, Computer Science Dept., Clemson University, Clemson, SC
http://www.cs.clemson.edu/~mark/homepage.html